1. Field of the Invention
The present invention relates to a bias circuit for a bit line of a memory array in an integrated circuit.
2. Description of Related Art
In an operation to ascertain the contents of a memory cell, a bit line bias circuit applies a bias to a bit line of a memory array, and a word line applies a bias to a selected memory cell of a memory array. A sense current results between the bit line and a reference line on opposite sides of the memory cell, flowing through the memory cell with a magnitude depending on the data stored by the memory cell as represented by a threshold voltage of the memory cell.
However, the reference line, often referred to as a source line, is not an ideal reference line. The reference line has some finite resistance rather than zero resistance. The finite resistance causes an unwanted voltage difference between the intended reference voltage such as zero volts or ground, and the source of a memory cell. During a sensing operation, the word line bias is reduced in effect, as the voltage difference between the word line and the reference line is reduced. As a result, the result of sensing may be wrong. This effect becomes worse with increasing current, because the unwanted voltage difference is proportional to sense current (V=I*R). Larger scale integration worsens this problem, as larger numbers of bit lines—that can each contribute current to the reference line—are coupled to the same reference line.
One approach to this approach is multi-pass sensing, in which sensing in limited to only a subset of memory cells in the array that draw a current larger than a threshold current. In subsequent sensing passes, previously sensed cells are turned off. Due to the increased time of performing multiple passes, it would be desirable to eliminate multiple passes, or at least to reduce the number of sensing passes.